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ISL97671A
Theory of Operation
PWM Boost Converter
The current mode PWM boost converter produces the minimal
voltage needed to enable the LED stack with the highest forward
voltage drop to run at the programmed current. The ISL97671A
employs current mode control boost architecture that has a fast
current sense loop and a slow voltage feedback loop. Such
architecture achieves a fast transient response that is essential
for notebook backlight applications in which drained batteries
can be instantly changed to an AC/DC adapter without
noticeable visual disturbance. The number of LEDs that can be
driven by ISL97671A depends on the type of LED chosen in the
application. The ISL97671A is capable of boosting up to 45V and
typically driving 13 LEDs in series for each of the 6 channels,
enabling a total of 78 pieces of the 3.2V/20mA type of LEDs.
Enable
The EN pin is used to enable or disable the ISL97671A operation. It
Dynamic Headroom Control
The ISL97671A features a proprietary Dynamic Headroom
Control circuit that detects the highest forward voltage string or
effectively the lowest voltage from any of the CH0-CH5 pins.
When this lowest channel voltage is lower than the short circuit
threshold, V SC , such voltage will be used as the feedback signal
for the boost regulator. The boost makes the output to the correct
level such that the lowest channel pin is at the target headroom
voltage. Since all LED stacks are connected to the same output
voltage, the other channel pins will have a higher voltage, but the
regulated current source circuit on each channel will ensure that
each channel has the same programmed current. The output
voltage will regulate cycle-by-cycle and is always referenced to
the highest forward voltage string in the architecture.
MAXIMUM DC CURRENT SETTING
The initial brightness should be set by choosing an appropriate
value for R SET . This should be chosen to fix the maximum
possible LED current:
I LEDmax = ---------------
is a high voltage pin that can be tied directly to V IN up to 26.5V. If EN
is pulled low for longer than 30ms, the device will shut down.
410.5
R SET
(EQ. 1)
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the current
source circuit, as shown in Figure 19.
The LED peak current is set by translating the R SET current to the
output with a scaling factor of 410.5/R SET . The source terminals
of the current source MOSFETs are designed to run at 500mV to
optimize power loss versus accuracy requirements. The sources
of errors of the channel-to-channel current matching come from
the op amps offset, internal layout, reference, and current source
resistors. These parameters are optimized for current matching
Once R SET is fixed, the LED DC current can be adjusted through
Register 0x07 (BRTDC) as follows:
I LED = 1.61x ( BRTDC ? R SET ) (EQ. 2)
BRTDC can be programmed from 0 to 255 in decimal and
defaults to 255 (0xFF). If left at the default value, LED current will
be fixed at I LEDmax . BRTDC can be adjusted dynamically on the fly
during operation. BRTDC = 0 disconnects all channels.
For example, if the maximum required LED current (I LED(max) ) is
20mA, rearranging Equation 1 yields Equation 3:
and absolute current accuracy. On the other hand, the absolute
accuracy is additionally determined by the external R SET , and
therefore, additional tolerance will be contributed by the current
setting resistor. A 1% tolerance resistor is therefore
recommended.
R SET = 410.5 ? 0.02 = 20.52k Ω
If BRTDC is set to 200 then:
I LED = 1.61 ? 200 ? 20100 = 16.02mA
(EQ. 3)
(EQ. 4)
PWM DIMMING CONTROL
The ISL97671A provides multiple PWM dimming methods, as
described in the following. Table 1 summarizes the dimming
mode selection. Each of these methods results in PWM chopping
of the current in the LEDs for all 6 channels to provide a lower
average LED current. During the On periods, the LED current will
be defined by the value of R SET and BRTDC, as described in
Equations 1 and 2. The source of the PWM signal can be
+
described as follows:
+
-
REF
-
1. Internally generated 256 step duty cycle BRT register
programmed through the SMBus/I 2 C.
RSET
+
-
PWM DIMMING
DC DIMMING
FIGURE 19. SIMPLIFIED CURRENT SOURCE CIRCUIT
11
2. External signal from PWM.
3. DPST mode. Internally generated signal with duty cycle
defined by the product of the PWM input duty cycle and
SMBus/I 2 C programmed BRT register.
4. Direct PWM mode. The output duty cycle and dimming
frequency follow the input PWM signal.
The default PWM dimming mode is in DPST. In all of the
methods, the average LED channel current is controlled by I LED
FN7709.3
November 30, 2012
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